Invention Grant
- Patent Title: Method of spacer-defined direct patterning in semiconductor fabrication
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Application No.: US15900425Application Date: 2018-02-20
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Publication No.: US10658181B2Publication Date: 2020-05-19
- Inventor: Toshihisa Nozawa , Dai Ishikawa , Tomohiro Kubota
- Applicant: ASM IP Holding B.V.
- Applicant Address: NL Almere
- Assignee: ASM IP Holding B.V.
- Current Assignee: ASM IP Holding B.V.
- Current Assignee Address: NL Almere
- Agency: Snell & Wilmer L.L.P.
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/027 ; H01L21/033 ; H01L21/311 ; H01L21/3213 ; H01L21/768

Abstract:
A method of spacer-defined direct patterning in semiconductor fabrication includes: providing a photoresist structure having a target width of lines; trimming the photoresist structures such that a width of each trimmed photoresist structure is smaller than the target width; depositing an oxide film on the template, thereby entirely covering with the oxide film an exposed top surface of the template and the trimmed photoresist structures; etching the oxide film-covered template to remove an unwanted portion of the oxide film without removing the trimmed photoresist structures so as to form vertical spacers isolated from each other, each spacer substantially maintaining the target width and being constituted by the trimmed photoresist structures and a vertical portion of the oxide film covering sidewalls of the trimmed photoresist structures; and etching the spacer-formed template to transfer a pattern constituted by the spacers to the template.
Public/Granted literature
- US20190259612A1 METHOD OF SPACER-DEFINED DIRECT PATTERNING IN SEMICONDUCTOR FABRICATION Public/Granted day:2019-08-22
Information query
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