A clock voltage step-up circuit comprises a first inverter, a second inverter, a third inverter, a PMOS transistor, and a bootstrap capacitor. An input end of the first inverter is used for inputting a first clock signal. An input end of the second inverter is connected to an output end of the first inverter, and an output end of the second inverter outputs a first control signal used for controlling a sampling switch; and after the first control signal passes through a fourth inverter, a fifth inverter and a sixth inverter, a second control signal used for controlling the sampling switch is generated. An input end of the third inverter is connected to a second clock signal, and the first clock signals and the second clock signals are a set of clock signals, every two of which are not overlapped.