公开(公告)号：US10566990B2

公开(公告)日：2020-02-18

申请号：US16344734

申请日：2017-11-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chuan Luo

IPC: H03M1/66 ,  H03M1/68 ,  H03K19/20 ,  H03M1/80 ,  H03M1/06 ,  H03M1/00

Abstract: A segmented resistor string type digital to analog converter comprises: a most significant bit (MSB) resistor string (104) comprising a high level resistor string, an intermediate level resistor string and a ground level resistor string; a decoding circuit (101), configured to decode an n-bit code of the MSB resistor string (104) and output 2n decoded codes; a logic sequential generation circuit (102), connected to the decoding circuit (101) and configured to perform a logic operation on a middle-position code among the 2n decoded codes and a refresh clock signal in non-overlapping sequences, and output two groups of control signals with completely complementary high level durations; a control signal bootstrap circuit (103), connected to the logic sequential generation circuit (102) and configured to perform bootstrap processing on the control signal, and increase the high level of the control signal to a sum of a power supply voltage and a threshold voltage; and a first switch group (106), connected to the control signal bootstrap circuit (103) and the intermediate level resistor string, where on/off of the first switch group (106) is controlled by the control signal after the bootstrap processing, so as to connect the intermediate level resistor string to the circuit or disconnect the intermediate level resistor string from the circuit.

公开(公告)号：US10659040B2

公开(公告)日：2020-05-19

申请号：US16328402

申请日：2017-08-22

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chuan Luo

IPC: H03K17/06 ,  H03K17/687 ,  H03K5/02

Abstract: A clock voltage step-up circuit comprises a first inverter, a second inverter, a third inverter, a PMOS transistor, and a bootstrap capacitor. An input end of the first inverter is used for inputting a first clock signal. An input end of the second inverter is connected to an output end of the first inverter, and an output end of the second inverter outputs a first control signal used for controlling a sampling switch; and after the first control signal passes through a fourth inverter, a fifth inverter and a sixth inverter, a second control signal used for controlling the sampling switch is generated. An input end of the third inverter is connected to a second clock signal, and the first clock signals and the second clock signals are a set of clock signals, every two of which are not overlapped.

公开(公告)号：US10236876B2

公开(公告)日：2019-03-19

申请号：US15748156

申请日：2016-05-11

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chuan Luo

IPC: H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K17/10 ,  H03K19/0175

Abstract: A switch control circuit includes: a clock circuit (110) configured to generate a first clock control signal (CLK1) and a second clock control signal (CLK2); a voltage boosting circuit (120) configured to receive the second clock control signal (CLK2) and an operating voltage outputted by the power source (VDD); and boost the operating voltage by a preset value to form a switch control signal (H1) under the control of the second clock control signal (CLK2); and an inverting circuit (130) configured to receive the first clock control signal (CLK1) and the switch control signal (H1), and determine whether or not to output the switch control signal (H1) to the switch circuit according to the first clock control signal (CLK1), so as to control on/off of the switch circuit.