Invention Grant
- Patent Title: Quantum circuit assemblies with vertically-stacked parallel-plate capacitors
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Application No.: US16011829Application Date: 2018-06-19
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Publication No.: US10665769B2Publication Date: 2020-05-26
- Inventor: Roman Caudillo , Zachary R. Yoscovits , Lester Lampert , David J. Michalak , Jeanette M. Roberts , Ravi Pillarisetty , Hubert C. George , Nicole K. Thomas , James S. Clarke
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patnet Capital Group
- Main IPC: H01L39/02
- IPC: H01L39/02 ; H01L27/18 ; H01L39/24 ; H01L39/04 ; G06N10/00 ; H01L39/22

Abstract:
Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.
Public/Granted literature
- US20190044046A1 QUANTUM CIRCUIT ASSEMBLIES WITH VERTICALLY-STACKED PARALLEL-PLATE CAPACITORS Public/Granted day:2019-02-07
Information query
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