公开(公告)号：US11922274B1

公开(公告)日：2024-03-05

申请号：US17323487

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Hubert C. George ,  James S. Clarke ,  Ravi Pillarisetty ,  Brennen Karl Mueller ,  Stephanie A. Bojarski ,  Eric M. Henry ,  Roza Kotlyar ,  Thomas Francis Watson ,  Lester Lampert ,  Samuel Frederick Neyens

IPC: G06N10/00 ,  H01L29/775 ,  H01L29/12 ,  H01L27/088

CPC classification number: G06N10/00 ,  H01L27/088 ,  H01L29/122 ,  H01L29/775

Abstract: Quantum dot devices with three of more accumulation gates provided over a single row of a quantum dot formation region are disclosed. Each accumulation gate is electrically coupled to a respective doped region. In this manner, multiple single electron transistors (SETs) are provided along the row. Side and/or center screening gates may be used to apply microwave pulses for qubit control and to control electrostatics so that source and drain regions of the multiple SETs with quantum dots formed along the single row of a quantum dot formation region are sufficiently isolated from one another. Such quantum dot devices provide strong spatial localization of the quantum dots, good control over quantum dot interactions and manipulation, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

公开(公告)号：US11749721B2

公开(公告)日：2023-09-05

申请号：US16146899

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/00 ,  H01L29/15 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  G06N10/00 ,  H01L29/82 ,  B82Y10/00 ,  H01L29/76 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/778 ,  H01L29/165 ,  H01L29/12

CPC classification number: H01L29/157 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/02362 ,  H01L29/401 ,  H01L29/42312 ,  H01L29/42368 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/7831 ,  H01L29/82 ,  H01L29/127 ,  H01L29/165 ,  H01L29/7782 ,  H01L29/7786

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.

公开(公告)号：US20230197833A1

公开(公告)日：2023-06-22

申请号：US17558207

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Payam Amin ,  Ravi Pillarisetty ,  Hubert C. George ,  James S. Clarke

IPC: H01L29/66 ,  H01L29/15 ,  H01L29/786 ,  H03K17/92 ,  G06N10/40

CPC classification number: H01L29/66977 ,  H01L29/158 ,  H01L29/78645 ,  H03K17/92 ,  G06N10/40 ,  H01L29/0665

Abstract: Quantum dot devices and related methods and systems that use semiconductor nanoribbons arranged in a grid where a plurality of first nanoribbons, substantially parallel to one another, intersect a plurality of second nanoribbons, also substantially parallel to one another but at an angle with respect to the first nanoribbons, are disclosed. Different gates at least partially wrap around individual portions of the first and second nanoribbons, and at least some of the gates are provided at intersections of the first and second nanoribbons. Unlike previous approaches to quantum dot formation and manipulation, nanoribbon-based quantum dot devices provide strong spatial localization of the quantum dots, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

公开(公告)号：US11682701B2

公开(公告)日：2023-06-20

申请号：US16367155

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Stephanie A. Bojarski ,  Hubert C. George ,  Sarah Atanasov ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Lester Lampert ,  Thomas Francis Watson ,  David J. Michalak ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/78 ,  H01L27/088 ,  H01L23/528 ,  G06N10/00 ,  H01L21/768 ,  H01L23/522 ,  H01L29/66

CPC classification number: H01L29/122 ,  G06N10/00 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.

公开(公告)号：US11569428B2

公开(公告)日：2023-01-31

申请号：US16347097

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Adel A. Elsherbini ,  Shawna Liff ,  Johanna M. Swan ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Hubert C. George ,  James S. Clarke

IPC: H01L27/32 ,  H01L39/04 ,  G06N10/00 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L27/18 ,  B82Y10/00 ,  H01L23/538 ,  H01L29/66

Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

公开(公告)号：US11417765B2

公开(公告)日：2022-08-16

申请号：US16017942

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/78 ,  H01L23/522 ,  H01L29/66 ,  H01L29/76 ,  H01L29/12 ,  H01L29/40 ,  H01L29/423 ,  B82Y30/00 ,  B82Y10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

公开(公告)号：US20220216305A1

公开(公告)日：2022-07-07

申请号：US17704906

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L23/46 ,  H01L29/43 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/76 ,  H01L29/40

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US11355623B2

公开(公告)日：2022-06-07

申请号：US15924407

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas

IPC: H01L29/66 ,  H01L29/82 ,  H01L29/49 ,  H01L29/40 ,  G06N10/00 ,  H01L29/423 ,  H01L21/266 ,  B82Y10/00 ,  H01L29/76 ,  H01L21/265 ,  B82Y30/00 ,  B82Y40/00

Abstract: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.

公开(公告)号：US11335778B2

公开(公告)日：2022-05-17

申请号：US16018751

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L23/46 ,  H01L29/43 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/76 ,  H01L29/40 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L21/311 ,  H01L29/778 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US20220013658A1

公开(公告)日：2022-01-13

申请号：US17472015

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.