公开(公告)号：US11569428B2

公开(公告)日：2023-01-31

申请号：US16347097

申请日：2016-12-27

申请人： Intel Corporation

发明人： Jeanette M. Roberts ,  Adel A. Elsherbini ,  Shawna Liff ,  Johanna M. Swan ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Hubert C. George ,  James S. Clarke

IPC分类号： H01L27/32 ,  H01L39/04 ,  G06N10/00 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L27/18 ,  B82Y10/00 ,  H01L23/538 ,  H01L29/66

摘要： One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

公开(公告)号：US11417765B2

公开(公告)日：2022-08-16

申请号：US16017942

申请日：2018-06-25

申请人： Intel Corporation

发明人： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L29/78 ,  H01L23/522 ,  H01L29/66 ,  H01L29/76 ,  H01L29/12 ,  H01L29/40 ,  H01L29/423 ,  B82Y30/00 ,  B82Y10/00

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

公开(公告)号：US20220216305A1

公开(公告)日：2022-07-07

申请号：US17704906

申请日：2022-03-25

申请人： Intel Corporation

发明人： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC分类号： H01L29/12 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L23/46 ,  H01L29/43 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/76 ,  H01L29/40

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US11355623B2

公开(公告)日：2022-06-07

申请号：US15924407

申请日：2018-03-19

申请人： Intel Corporation

发明人： Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas

IPC分类号： H01L29/66 ,  H01L29/82 ,  H01L29/49 ,  H01L29/40 ,  G06N10/00 ,  H01L29/423 ,  H01L21/266 ,  B82Y10/00 ,  H01L29/76 ,  H01L21/265 ,  B82Y30/00 ,  B82Y40/00

摘要： Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.

公开(公告)号：US11335778B2

公开(公告)日：2022-05-17

申请号：US16018751

申请日：2018-06-26

申请人： Intel Corporation

发明人： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC分类号： H01L29/12 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L23/46 ,  H01L29/43 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/76 ,  H01L29/40 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L21/311 ,  H01L29/778 ,  H01L29/82

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US20220013658A1

公开(公告)日：2022-01-13

申请号：US17472015

申请日：2021-09-10

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC分类号： H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US20210408271A1

公开(公告)日：2021-12-30

申请号：US17468090

申请日：2021-09-07

申请人： Intel Corporation

发明人： Hubert C. George ,  James S. Clarke

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

摘要： Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes; a plurality of islands, disposed between the first and second S/D electrodes; and dielectric material disposed between adjacent ones of the islands, between the first S/D electrode and an adjacent one of the islands, and between the second S/D electrode and an adjacent one of the islands.

公开(公告)号：US11107891B2

公开(公告)日：2021-08-31

申请号：US16650299

申请日：2017-12-23

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Kanwaljit Singh ,  Roza Kotlyar ,  Patrick H. Keys ,  James S. Clarke

IPC分类号： H01L29/15 ,  G06N10/00 ,  B82Y10/00

摘要： Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.

公开(公告)号：US11101352B2

公开(公告)日：2021-08-24

申请号：US16328615

申请日：2016-09-24

申请人： Intel Corporation

发明人： Hubert C. George ,  Ravi Pillarisetty ,  Jeanette M. Roberts ,  Nicole K. Thomas ,  James S. Clarke

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L29/12 ,  H01L29/423 ,  H01L29/76 ,  B82Y10/00 ,  B82Y40/00 ,  H01L23/532

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

公开(公告)号：US10804399B2

公开(公告)日：2020-10-13

申请号：US16323682

申请日：2016-09-24

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Jeanette M. Roberts ,  Nicole K. Thomas ,  Hubert C. George ,  James S. Clarke

IPC分类号： H01L21/44 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack with first and second quantum well layers, a first set of gates disposed on the quantum well stack such that the first quantum well layer is disposed between the barrier layer and the first set of gates, a first set of conductive pathways extending from the first set of gates to a first face of the quantum dot device, a second set of gates disposed on the quantum well stack such that the second quantum well layer is disposed between the barrier layer and the second set of gates, and a second set of conductive pathways extending from the second set of gates to a second face of the quantum dot device, wherein the second face is different from the first face.