- 专利标题: Mitigation of error correction failure due to trapping sets
-
申请号: US16225272申请日: 2018-12-19
-
公开(公告)号: US10666295B1公开(公告)日: 2020-05-26
- 发明人: Ludovic Danjean , Sundararajan Sankaranarayanan , Ivana Djurdjevic , AbdelHakim Alhussien , Erich F. Haratsch
- 申请人: Seagate Technology LLC
- 申请人地址: US CA Fremont
- 专利权人: Seagate Technology LLC
- 当前专利权人: Seagate Technology LLC
- 当前专利权人地址: US CA Fremont
- 代理机构: Setter Roche LLP
- 代理商 Kirk A Cesari
- 主分类号: H03M13/11
- IPC分类号: H03M13/11 ; G06F11/10 ; H03M13/00
摘要:
An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.
信息查询
IPC分类: