公开(公告)号：US10177787B1

公开(公告)日：2019-01-08

申请号：US14856674

申请日：2015-09-17

Applicant: Seagate Technology LLC

Inventor： Ludovic Danjean ,  Sundararajan Sankaranarayanan ,  Ivana Djurdjevic ,  AbdelHakim Alhussien ,  Erich F. Haratsch

IPC: H03M13/11 ,  H03M13/00 ,  G06F11/10

Abstract: An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.

公开(公告)号：US10666295B1

公开(公告)日：2020-05-26

申请号：US16225272

申请日：2018-12-19

Applicant: Seagate Technology LLC

Inventor： Ludovic Danjean ,  Sundararajan Sankaranarayanan ,  Ivana Djurdjevic ,  AbdelHakim Alhussien ,  Erich F. Haratsch

IPC: H03M13/11 ,  G06F11/10 ,  H03M13/00

Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.

公开(公告)号：US10263640B2

公开(公告)日：2019-04-16

申请号：US15478895

申请日：2017-04-04

Applicant: Seagate Technology LLC

Inventor： Ivana Djurdjevic ,  Ara Patapoutian ,  Zheng Wang ,  AbdelHakim Alhussien ,  Sundararajan Sankaranarayanan ,  Ludovic Danjean ,  Erich F. Haratsch

IPC: H03M13/11

Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.

公开(公告)号：US20180287635A1

公开(公告)日：2018-10-04

申请号：US15478895

申请日：2017-04-04

Applicant: Seagate Technology LLC

Inventor： Ivana Djurdjevic ,  Ara Patapoutian ,  Zheng Wang ,  AbdelHakim Alhussien ,  Sundararajan Sankaranarayanan ,  Ludovic Danjean ,  Erich F. Haratsch

IPC: H03M13/11

CPC classification number: H03M13/1111

Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.

公开(公告)号：US09319073B2

公开(公告)日：2016-04-19

申请号：US14194180

申请日：2014-02-28

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Ivana Djurdjevic ,  Yu Cai ,  Erich F. Haratsch ,  Yue Li ,  Earl T. Cohen

IPC: H04L1/00 ,  H03M13/35 ,  G06F11/10 ,  H03M13/09 ,  H03M13/11 ,  H03M13/13 ,  H03M13/29

CPC classification number: H03M13/35 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/2906

Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

Abstract translation: 一种装置包括控制器和自适应纠错码解码器。 控制器可以被配置为从存储器设备读取数据并写入数据。 控制器还可以被配置为以两步过程写入数据，其包括（i）在将数据写入最低有效位（LSB）页面之后，使用第一强度纠错码（LSB）检查存储在LSB页中的数据 ECC）解码过程，并且（ii）在将数据写入与LSB页面相关联的最高有效位（MSB）页面之后，使用第二强度纠错码（ECC）解码处理来检查存储在LSB和MSB页面中的数据。

公开(公告)号：US11233528B1

公开(公告)日：2022-01-25

申请号：US17022549

申请日：2020-09-16

Applicant: Seagate Technology LLC

Inventor： Ivana Djurdjevic ,  Ara Patapoutian ,  Deepak Sridhara ,  Bengt Anders Ulriksson ,  Jeffrey John Pream

IPC: H03M13/11

Abstract: A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.

公开(公告)号：US09354816B2

公开(公告)日：2016-05-31

申请号：US14269590

申请日：2014-05-05

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  Gordon J. Coleman ,  Earl T. Cohen ,  Ivana Djurdjevic ,  Erich F. Haratsch

IPC: G11C29/00 ,  G06F3/06 ,  H03M13/11

CPC classification number: G06F3/0617 ,  G06F3/0632 ,  G06F3/0679 ,  H03M13/1108

Abstract: An apparatus includes a plurality of memory dies and a controller. The controller may be communicatively coupled to the plurality of memory dies and configured to utilize multiple copies of a root record containing system data during a boot-up process. The multiple copies of the root record are stored using at least two of the plurality of memory dies.

Abstract translation: 一种装置包括多个存储器管芯和一个控制器。 控制器可以通信地耦合到多个存储器管芯并且被配置为在引导过程期间利用包含系统数据的根记录的多个副本。 使用多个存储器管芯中的至少两个来存储根记录的多个拷贝。