Invention Grant
- Patent Title: Methods of forming self aligned spacers for nanowire device structures
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Application No.: US15778724Application Date: 2015-12-24
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Publication No.: US10672868B2Publication Date: 2020-06-02
- Inventor: Karthik Jambunathan , Glenn Glass , Anand Murthy , Jun Sung Kang , Seiyon Kim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard, & Mughal LLP
- International Application: PCT/US2015/000420 WO 20151224
- International Announcement: WO2017/111850 WO 20170629
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; B82Y10/00 ; H01L29/417 ; H01L29/66 ; H01L29/775 ; H01L29/08 ; H01L29/786 ; H01L29/423

Abstract:
Methods of forming self-aligned nanowire spacer structures are described. An embodiment includes forming a channel structure comprising a first nanowire and a second nanowire. Source/drain structures are formed adjacent the channel structure, wherein a liner material is disposed on at least a portion of the sidewalls of the source/drain structures. A nanowire spacer structure is formed between the first and second nanowires, wherein the nanowire spacer comprises an oxidized portion of the liner.
Public/Granted literature
- US20180358436A1 METHODS OF FORMING SELF ALIGNED SPACERS FOR NANOWIRE DEVICE STRUCTURES Public/Granted day:2018-12-13
Information query
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