Structures for measuring RIE lag depth of a semiconductor device, including: a first metal layer; a dielectric cap layer on top of the first metal layer; an electrical ground element formed beneath one or more portions of the dielectric cap layer and within the first metal layer, the electrical ground element being electrically grounded; and a second metal layer on top of the dielectric cap layer, the second metal layer having an array of one or more sub-arrays of metal wires, each sub-array being connected to a respective bond pad and having metal wires of a given width; wherein a distance from a bottom surface of the array of metal wires to a top surface of the dielectric cap layer is indicative of RIE lag depth. The disclosure also relates to methods and systems for measuring RIE lag depth and identifying the existence of an electrical short of a semiconductor device.