Invention Grant
- Patent Title: Self-aligning source, drain and gate process for III-V nitride MISHEMTs
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Application No.: US15551821Application Date: 2016-03-09
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Publication No.: US10679860B2Publication Date: 2020-06-09
- Inventor: Lakshmi Kanta Bera , Yee Chong Loke , Surani Bin Dolmanan , Sudhiranjan Tripathy , Wai Hoe Tham
- Applicant: Agency for Science, Technology and Research
- Applicant Address: SG Singapore
- Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
- Current Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
- Current Assignee Address: SG Singapore
- Agency: Choate, Hall & Stewart LLP
- Agent Brian E. Reese; Dana M. Daukss
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@25b01357
- International Application: PCT/SG2016/050111 WO 20160309
- International Announcement: WO2016/144263 WO 20160915
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/285 ; H01L29/51 ; H01L29/20 ; H01L29/778 ; H01L21/28 ; H01L29/205 ; H01L29/40 ; H01L29/45 ; H01L29/49
Abstract:
A method for fabrication of high electron mobility transistor (HEMT) semiconductor devices is presented. The method includes providing a substrate, growing a HEMT layer structure on the substrate; and self-aligned common metal stack formation of source, drain and gate electrodes on the HEMT layer structure using a single lithographic mask.
Public/Granted literature
- US20180033631A1 SELF-ALIGNING SOURCE, DRAIN AND GATE PROCESS FOR III-V NITRIDE MISHEMTS Public/Granted day:2018-02-01
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