Invention Grant
- Patent Title: Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs
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Application No.: US16375218Application Date: 2019-04-04
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Publication No.: US10680061B2Publication Date: 2020-06-09
- Inventor: Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Xin Miao
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/06 ; H01L29/66 ; H01L29/08 ; H01L29/423 ; H01L29/10 ; H01L21/84 ; H01L29/417 ; H01L29/78
Abstract:
Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Spacers are formed, with at least one top pair of spacers being positioned above an uppermost channel layer. The top pair of spacers each has a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.
Public/Granted literature
- US20190237541A1 SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FORMATION IN STACKED-CHANNEL FETS Public/Granted day:2019-08-01
Information query
IPC分类:
