Invention Grant
- Patent Title: Testing for memories during mission mode self-test
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Application No.: US16012455Application Date: 2018-06-19
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Publication No.: US10706952B1Publication Date: 2020-07-07
- Inventor: Steven Lee Gregor , Patrick Gallagher
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee Address: US CA San Jose
- Agency: Tarolli, Sundheim, Covell & Tummino LLP
- Main IPC: G11C29/44
- IPC: G11C29/44 ; G11C29/20 ; G11C29/36 ; G11C29/42

Abstract:
Systems and methods disclosed herein provide for efficiently testing memories during mission mode self-test (“MMST”) without destroying any original functional data. Embodiments provide for a converter to feed a manipulated version of the original functional data back into the tested memories. Embodiments further provide an accumulator to count the occurrences of correctable and uncorrectable errors associated with the tested memories.
Information query