公开(公告)号：US10706952B1

公开(公告)日：2020-07-07

申请号：US16012455

申请日：2018-06-19

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Patrick Gallagher

IPC: G11C29/44 ,  G11C29/20 ,  G11C29/36 ,  G11C29/42

Abstract: Systems and methods disclosed herein provide for efficiently testing memories during mission mode self-test (“MMST”) without destroying any original functional data. Embodiments provide for a converter to feed a manipulated version of the original functional data back into the tested memories. Embodiments further provide an accumulator to count the occurrences of correctable and uncorrectable errors associated with the tested memories.

公开(公告)号：US10482989B1

公开(公告)日：2019-11-19

申请号：US15903916

申请日：2018-02-23

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/38 ,  G11C29/44

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a two-pass diagnostic test of the target memory, wherein, in the first pass, a data compare unit provides clock cycle values associated with detected mis-compares to a tester, and, in the second pass, the data compare unit extracts data vectors associated with the clock cycle values. Embodiments further provide for a bit fail map report that is generated based on the extracted data vectors.

公开(公告)号：US10192013B1

公开(公告)日：2019-01-29

申请号：US15376394

申请日：2016-12-12

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Ankit Bandejia ,  Navneet Kaushik ,  Steven Lee Gregor

IPC: G06F17/50 ,  G11C29/12

Abstract: Electronic design automation (EDA) systems, methods, and computer readable media are presented for adding design for test (DFT) logic at register transfer level (RTL) into an integrated circuit (IC) design at RTL. In some embodiments, the DFT logic at RTL includes a port that connects to a hierarchical reference with a hierarchical path in the tree structure hierarchy to a part of the IC design at RTL. Such DFT modification helps to decrease the number of new ports added at this stage, and as a result assists subsequent debugging and back-annotation of RTL.

公开(公告)号：US10706950B1

公开(公告)日：2020-07-07

申请号：US16012435

申请日：2018-06-19

Applicant: Cadence Design Systems, Inc.

Inventor： Patrick Gallagher ,  Steven Lee Gregor

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/46 ,  G11C29/44

Abstract: Systems and methods disclosed herein provide for improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”). Embodiments provide for a masking element to inject one or more faults into the ECC logic during at least one of a manufacturing test (“MFGT”) and a power-on-self-test (“POST”), wherein, based on the injected faults, it can be determined if the ECC logic contains any errors.

公开(公告)号：US10395747B1

公开(公告)日：2019-08-27

申请号：US15642004

申请日：2017-07-05

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/00 ,  G11C29/14 ,  G06F17/50

Abstract: An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s).

公开(公告)号：US09640280B1

公开(公告)日：2017-05-02

申请号：US14930316

申请日：2015-11-02

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Navneet Kaushik ,  Steven Lee Gregor ,  Norman Card

IPC: G01R31/317 ,  G11C29/38 ,  G01R31/3177 ,  G11C29/10 ,  G11C29/12 ,  G06F17/50

CPC classification number: G11C29/38 ,  G01R31/3177 ,  G06F17/5081 ,  G06F2217/14 ,  G11C29/10 ,  G11C29/12

Abstract: Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the corresponding power domain in parallel. Once testing of memories within a particular power domain is over, the test circuitry tests memories belonging to another power domain in parallel, and so on.

公开(公告)号：US10319459B1

公开(公告)日：2019-06-11

申请号：US15636332

申请日：2017-06-28

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G01R31/317

Abstract: An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group (“JTAG”) controller may be coupled to the AMU(s), which can be configured to access logic of the programmed testplan algorithm(s). A direct access controller (DAC) can be coupled to the AMU(s), which can be configured to access internal nodes in the AMU(s). The DAC can be configured to activate the programmed testplan algorithm(s) using a minimally direct access pin interface in the AMU(s).

公开(公告)号：US09865362B1

公开(公告)日：2018-01-09

申请号：US15019504

申请日：2016-02-09

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Steven Lee Gregor ,  Norman Robert Card ,  Navneet Kaushik

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/02 ,  G11C29/44

Abstract: Method and apparatus for testing the memory components of an integrated Circuit (IC) using a routing logic and a built-in design for test (DFT) hardware processing device. Based on input provided from an interface controller to the IC, the IC is tested according to one of at least two modes. In a first mode, the built-in DFT hardware processing device executes a test that checks for faults in the physical memory of the IC. In a second mode, the built-in DFT hardware processing device executes a test that checks for faults in the error correction logic of the IC. By using the same routing logic and built-in DFT hardware processing device, tests of the memory components according to the first and second mode can be executed on an automatic and serial basis, even after the manufacture of the IC.

公开(公告)号：US10783299B1

公开(公告)日：2020-09-22

申请号：US15936999

申请日：2018-03-27

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G06F30/00 ,  G06F30/3312 ,  G06F111/20 ,  G06F119/12

Abstract: An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.

公开(公告)号：US10699795B1

公开(公告)日：2020-06-30

申请号：US16020083

申请日：2018-06-27

Applicant: Cadence Design Systems, Inc.

Inventor： Norman Card ,  Steven Lee Gregor

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/38 ,  G11C29/18 ,  G06F30/327 ,  G11C29/04

Abstract: A method for identifying a physical memory(ies) associated with a logical memory(ies) in a memory design can include (a) receiving a generic netlist for the memory design, (b) generating a test mode for the memory using the generic netlist, (c) determining the logical memory(ies); (d) performing a simulation on the test mode for the logical memory(ies); and (e) identifying the physical memory(ies) by tracing chip selects for the physical memory(ies) to the logical memory(ies). The identifying the physical memory(ies) may further include identifying which chip selects are active. The identifying the physical memory(ies) can further include tracing an address and a data pin(s) for the logical memory(ies) in the simulation. The identifying the physical memory(ies) can further include determining an address and a data pin(s) for the logical memory(ies) in the simulation.