公开(公告)号：US12099791B1

公开(公告)日：2024-09-24

申请号：US17490496

申请日：2021-09-30

申请人： Cadence Design Systems, Inc.

发明人： Shadi Saba ,  Roque Alejandro Arcudia Hernandez ,  Uyen Huynh Ha Nguyen ,  Pedro Eugênio Rocha Medeiros ,  Claire Liyan Ying ,  Ruozhi Zhang ,  Gustavo Emanuel Faria Araujo

IPC分类号： G06F30/333

CPC分类号： G06F30/333

摘要： An approach is disclosed herein for test sequence processing that is applicable to machine learning model generated test sequences as disclosed herein. The test sequence processing includes classification, grouping, and filtering. The classification is generated based on the execution of the test sequences. The grouping is performed based on information captured during the classification of the test sequences. The filtering is performed on a group by group basis to remove redundant test sequences.

公开(公告)号：US12086529B1

公开(公告)日：2024-09-10

申请号：US17691974

申请日：2022-03-10

申请人： Cadence Design Systems, Inc.

发明人： Igor Keller ,  Eric K. Anderson ,  Yang Gao

IPC分类号： G06F30/398 ,  G06F30/3315 ,  G06F119/02

CPC分类号： G06F30/398 ,  G06F30/3315 ,  G06F2119/02

摘要： Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.

公开(公告)号：US20240296269A1

公开(公告)日：2024-09-05

申请号：US18178463

申请日：2023-03-03

申请人： Cadence Design Systems, Inc.

发明人： Mitchell G. Poplack ,  Bhoumik Shah ,  Jennifer Lee

IPC分类号： G06F30/3308

CPC分类号： G06F30/3308

摘要： The systems and methods described herein include emulators that implement wrappers comprising instrumentation logic for the emulator components (e.g., memories) to perform certain memory-related functions. These functions allow the physical binary memories of the emulator to behave as a ternary memory. The memory wrappers include instrumentation logic around logic of the physical binary memories. In some cases, embodiments generate the wrappers for the user memory, rather than performing conventional synthesis functions for user-design memories. The inputs include the user ternary RTL, as well as additional potential inputs for pre-compiler control. The wrappers instantiate the operations, such as MPRs or MPWs, and create the ternary-memory support logic to, for example, prevent unknown-value writes and to output unknown values X for unknown-value reads.

公开(公告)号：US11983538B2

公开(公告)日：2024-05-14

申请号：US17659569

申请日：2022-04-18

申请人： Cadence Design Systems, Inc.

发明人： Robert T. Golla ,  Ajay A. Ingle

IPC分类号： G06F9/38 ,  G06F12/0855

CPC分类号： G06F9/3834 ,  G06F12/0855

摘要： Techniques are disclosed relating to a processor load-store unit. In some embodiments, the load-store unit is configured to execute load/store instructions in parallel using first and second pipelines and first and second tag memory arrays. In tag write conflict situations, the load-store unit may arbitrate between the first and second pipelines to ensure the first and second tag memory array contents remain identical. In some embodiments, a data cache tag replay scheme is utilized. In some embodiments, executing load/store instructions in parallel with fills, probes, and store-updates, using separate but identical tag memory arrays, may advantageously improve performance.

公开(公告)号：US11947887B1

公开(公告)日：2024-04-02

申请号：US17953618

申请日：2022-09-27

申请人： Cadence Design Systems, Inc.

发明人： Krishna Chakravadhanula ,  Brian Foutz ,  Prateek Kumar Rai ,  Sarthak Singhal ,  Christos Papameletis ,  Vivek Chickermane

IPC分类号： G06F30/333 ,  G06F30/327 ,  G01R31/3185

CPC分类号： G06F30/333 ,  G06F30/327 ,  G01R31/318583

摘要： A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

公开(公告)号：US11900135B1

公开(公告)日：2024-02-13

申请号：US16212363

申请日：2018-12-06

申请人： CADENCE DESIGN SYSTEMS, INC.

发明人： Mitchell G Poplack ,  Yuhei Hayashi

IPC分类号： G06F3/00 ,  G06F9/455

CPC分类号： G06F9/45504

摘要： An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

公开(公告)号：US11893336B1

公开(公告)日：2024-02-06

申请号：US17499414

申请日：2021-10-12

申请人： CADENCE DESIGN SYSTEMS, INC.

发明人： Arvind Chokhani ,  Joseph Michael Swenton ,  Martin Thomas Amodeo

IPC分类号： G06F30/398 ,  G06F119/18 ,  G06F119/12

CPC分类号： G06F30/398 ,  G06F2119/12 ,  G06F2119/18

摘要： An IC test engine generates a plurality of two-cycle delay test patterns that target a first set of multicycle faults and/or defects of a fabricated IC chip based on an IC design. Each two-cycle delay test pattern includes a scan-in shift window operating at a test clock frequency, and a capture window with a launch cycle and a capture cycle operating at a functional clock frequency. The IC test engine fault simulates the plurality of two-cycle delay test patterns against a second set of multicycle faults and/or defects in the IC design utilizing sim-shifting, such that a state of the IC design after at least a last two shift clock cycles of a scan-in shift in window of each two-cycle delay test pattern of the plurality of two-cycle delay test patterns are fault simulated to provide two fault initialization cycles for detection of a multicycle delay fault and/or defect.

公开(公告)号：US11876650B2

公开(公告)日：2024-01-16

申请号：US17978422

申请日：2022-11-01

申请人： Cadence Design Systems, Inc.

发明人： Prashant Choudhary ,  Nanyang Wang

IPC分类号： H04L25/03

CPC分类号： H04L25/03076 ,  H04L25/03318

摘要： An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate. The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

公开(公告)号：US11861452B1

公开(公告)日：2024-01-02

申请号：US16443634

申请日：2019-06-17

申请人： Cadence Design Systems, Inc.

发明人： Ming Kai Hsu

IPC分类号： G06N3/063 ,  G10L25/30 ,  G06F17/18 ,  G06N3/047

CPC分类号： G06N3/063 ,  G06F17/18 ,  G06N3/047 ,  G10L25/30

摘要： Quantized softmax layers in neural networks are described. Some embodiments involve receiving, at an input to a softmax layer of a neural network from an intermediate layer of the neural network, a non-normalized output comprising a plurality of intermediate network decision values. Then for each intermediate network decision value of the plurality of intermediate network decision values, the embodiment involves: calculating a difference between the intermediate network decision value and a maximum network decision value; requesting, from a lookup table, a corresponding lookup table value using the difference between the intermediate network decision value and the maximum network decision value; and selecting the corresponding lookup table value as a corresponding decision value. A normalized output is then generated comprising the corresponding lookup table value for said each intermediate network decision value of the plurality of intermediate network decision values.

公开(公告)号：US11831153B1

公开(公告)日：2023-11-28

申请号：US16940679

申请日：2020-07-28

申请人： Cadence Design Systems, Inc.

发明人： Phalguni Bala ,  Manjunath Karikatti ,  Navin Kumar Mishra

IPC分类号： H02H9/04 ,  H01L25/18 ,  H03H7/01

CPC分类号： H02H9/046 ,  H01L25/18 ,  H03H7/0115 ,  H03H2210/026

摘要： A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (π) filter that enhances signaling bandwidth at the target signaling rate of the IC die. The signal driver may be implemented with output-stage data serialization circuitry disposed in series between source terminals of a thick-oxide drive transistor and a power rail to avoid explicit level-shifting circuitry between the relatively low core voltage domain and relatively high I/O voltage domain.