公开(公告)号：US10706950B1

公开(公告)日：2020-07-07

申请号：US16012435

申请日：2018-06-19

Applicant: Cadence Design Systems, Inc.

Inventor： Patrick Gallagher ,  Steven Lee Gregor

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/46 ,  G11C29/44

Abstract: Systems and methods disclosed herein provide for improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”). Embodiments provide for a masking element to inject one or more faults into the ECC logic during at least one of a manufacturing test (“MFGT”) and a power-on-self-test (“POST”), wherein, based on the injected faults, it can be determined if the ECC logic contains any errors.

公开(公告)号：US09170301B1

公开(公告)日：2015-10-27

申请号：US13772245

申请日：2013-02-20

Applicant: Cadence Design Systems, Inc.

Inventor： Patrick Gallagher ,  Krishna Chakravadhanula ,  Rajesh Khurana

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3177

CPC classification number: G01R31/31813 ,  G01R31/3177 ,  G01R31/318544 ,  G01R31/318575

Abstract: A method and apparatus for hierarchical compaction of test patterns to be applied to an integrated circuit during test is disclosed. The embodiments apply a hierarchical strategy for categorizing test patterns for compaction. A test pattern is considered against a series of criteria for a compacted test pattern. Where all the criteria are met the test pattern is merged into a compacted test pattern. If the criteria are not all met the test patterns are considered against each of the compacted test patterns in turn. This is repeated for each test pattern to create a set of compacted test patterns conforming to the requirements of the criteria. This method and apparatus provides for fine grained control of low power constraints when testing integrated circuits, and includes benefits such as preventing damage during test from burnout and hot spots, and avoiding failures due to IR drop.

Abstract translation: 公开了一种用于在测试期间应用于集成电路的测试图案的分层压缩的方法和装置。 这些实施例应用分级策略来分类用于压实的测试模式。 针对压实测试模式的一系列标准考虑了测试模式。 在满足所有标准的情况下，测试图案被合并到压实的测试图案中。 如果不满足标准，则依次对每个压实的测试模式考虑测试模式。 对于每个测试图案重复这一点，以创建符合标准要求的一组压实测试图案。 该方法和装置在测试集成电路时提供对低功率约束的细粒度控制，并且包括诸如防止在烧坏和热点期间的测试期间的损坏以及避免由于IR下降引起的故障的益处。

公开(公告)号：US10706952B1

公开(公告)日：2020-07-07

申请号：US16012455

申请日：2018-06-19

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Patrick Gallagher

IPC: G11C29/44 ,  G11C29/20 ,  G11C29/36 ,  G11C29/42

Abstract: Systems and methods disclosed herein provide for efficiently testing memories during mission mode self-test (“MMST”) without destroying any original functional data. Embodiments provide for a converter to feed a manipulated version of the original functional data back into the tested memories. Embodiments further provide an accumulator to count the occurrences of correctable and uncorrectable errors associated with the tested memories.