Invention Grant
- Patent Title: Gate electrode having a capping layer
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Application No.: US15067047Application Date: 2016-03-10
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Publication No.: US10707319B2Publication Date: 2020-07-07
- Inventor: Gilbert Dewey , Mark L. Doczy , Suman Datta , Justin K. Brask , Matthew V. Metz
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/78 ; H01L29/51 ; H01L21/28 ; H01L21/8238 ; H01L29/49 ; H01L29/66

Abstract:
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.
Public/Granted literature
- US20160197159A1 GATE ELECTRODE HAVING A CAPPING LAYER Public/Granted day:2016-07-07
Information query
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