Invention Grant
- Patent Title: Layout of semiconductor transistor device
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Application No.: US15361479Application Date: 2016-11-27
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Publication No.: US10727234B2Publication Date: 2020-07-28
- Inventor: Zhibiao Zhou , Ding-Lung Chen , Xing Hua Zhang , Shan Liu , Runshun Wang , Chien-Fu Chen , Wei-Jen Wang , Chen-Hsien Hsu
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L27/11 ; H01L27/092 ; H01L29/06 ; H01L27/02 ; H01L21/8238

Abstract:
The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.
Public/Granted literature
- US20180151571A1 LAYOUT of SEMICONDUCTOR TRANSISTOR DEVICE Public/Granted day:2018-05-31
Information query
IPC分类: