- Patent Title: Multiple-stacked semiconductor nanowires and source/drain spacers
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Application No.: US15613339Application Date: 2017-06-05
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Publication No.: US10756174B2Publication Date: 2020-08-25
- Inventor: Mark Van Dal , Gerben Doornbos , Chung-Te Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L27/06 ; H01L27/092 ; H01L29/423 ; H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L29/66 ; H01L29/417 ; H01L21/8238 ; H01L21/822 ; H01L29/40 ; H01L29/08 ; H01L29/786 ; B82Y10/00 ; H01L29/775 ; H01L21/02
Abstract:
A semiconductor device includes a substrate, a gate structure, at least one nanowire, at least one epitaxy structure, and at least one source/drain spacer. The gate structure is disposed on the substrate. The nanowire extends through the gate structure. The epitaxy structure is disposed on the substrate and is in contact with the nanowire. The source/drain spacer is disposed between the epitaxy structure and the gate structure and is embedded in the epitaxy structure.
Public/Granted literature
- US20180315817A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2018-11-01
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