Invention Grant
- Patent Title: Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
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Application No.: US15679077Application Date: 2017-08-16
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Publication No.: US10756198B2Publication Date: 2020-08-25
- Inventor: Gilbert Dewey , Niloy Mukherjee , Matthew Metz , Jack T. Kavalieros , Nancy M. Zelick , Robert S. Chau
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Shcwabe, Williamson & Wyatt P.C.
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L29/51 ; H01L21/768 ; H01L23/485 ; H01L23/532 ; H01L29/49 ; H01L29/66 ; H01L29/78 ; H01L21/285 ; H01L21/324 ; H01L51/52 ; H01L31/0224 ; H01L21/04 ; H01L51/10 ; H01L51/44 ; H01L29/45 ; H01L45/00 ; H01L33/00 ; H01B1/12 ; H01L33/40
Abstract:
An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
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