- 专利标题： Integration of vertical-transport transistors and planar transistors
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申请号： US15868199申请日： 2018-01-11
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公开(公告)号： US10777465B2公开(公告)日： 2020-09-15
- 发明人: Ruilong Xie , Chun-chen Yeh , Kangguo Cheng , Tenko Yamashita
- 申请人： GLOBALFOUNDRIES Inc.
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES INC.
- 当前专利权人： GLOBALFOUNDRIES INC.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Thompson Hine LLP
- 代理商 Anthony Canale
- 主分类号： H01L21/8234
- IPC分类号： H01L21/8234 ; H01L29/78 ; H01L27/088 ; H01L29/66 ; H01L29/51
摘要：
Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.
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