发明授权
- 专利标题: Semiconductor device and method of forming embedded wafer level chip scale packages
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申请号: US15615693申请日: 2017-06-06
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公开(公告)号: US10777528B2公开(公告)日: 2020-09-15
- 发明人: Yaojian Lin , Pandi C. Marimuthu , Il Kwon Shim , Byung Joon Han
- 申请人: STATS ChipPAC Pte. Ltd.
- 申请人地址: SG Singapore
- 专利权人: STATS ChipPAC Pte. Ltd.
- 当前专利权人: STATS ChipPAC Pte. Ltd.
- 当前专利权人地址: SG Singapore
- 代理机构: Patent Law Group: Atkins and Associates, P.C.
- 代理商 Robert D. Atkins
- 主分类号: H01L21/56
- IPC分类号: H01L21/56 ; H01L21/786 ; H01L21/784 ; H01L23/00 ; H01L23/31 ; H01L21/782 ; H01L21/82 ; H01L21/78
摘要:
A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.
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