- 专利标题: Grouping and partitioning of properties for logic verification
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申请号: US16411193申请日: 2019-05-14
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公开(公告)号: US10789403B1公开(公告)日: 2020-09-29
- 发明人: Rohit Dureja , Jason Raymond Baumgartner , Alexander Ivrii , Robert Kanzelman
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 代理机构: Cantor Colburn LLP
- 代理商 Bryan Bortnick
- 主分类号: G06F30/327
- IPC分类号: G06F30/327 ; G06F9/50 ; G06F17/16
摘要:
Embodiments of the invention are directed to a computer-implemented method of logic verification. The method includes obtaining a netlist of a circuit comprising a plurality of observable gates. A first observable gate is grouped together with a second observable gate based on a portion of a fan-in logic of the first observable gate being equal to a portion of a fan-in logic of the second observable gate. The group is expanded by including a third observable gate, based on a first strongly connected component (SCC) in the group having a similarity greater than a first threshold to a second SCC in the fan-in logic of the third observable gate. The group is further expanded by including a fourth observable gate, based on the distance of a portion of the fan-in logic of the fourth observable gate from a fan-in logic of at least one observable gate in the group of observable gates.
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