公开(公告)号：US10789403B1

公开(公告)日：2020-09-29

申请号：US16411193

申请日：2019-05-14

申请人： International Business Machines Corporation

发明人： Rohit Dureja ,  Jason Raymond Baumgartner ,  Alexander Ivrii ,  Robert Kanzelman

IPC分类号： G06F30/327 ,  G06F9/50 ,  G06F17/16

摘要： Embodiments of the invention are directed to a computer-implemented method of logic verification. The method includes obtaining a netlist of a circuit comprising a plurality of observable gates. A first observable gate is grouped together with a second observable gate based on a portion of a fan-in logic of the first observable gate being equal to a portion of a fan-in logic of the second observable gate. The group is expanded by including a third observable gate, based on a first strongly connected component (SCC) in the group having a similarity greater than a first threshold to a second SCC in the fan-in logic of the third observable gate. The group is further expanded by including a fourth observable gate, based on the distance of a portion of the fan-in logic of the fourth observable gate from a fan-in logic of at least one observable gate in the group of observable gates.