Invention Grant
- Patent Title: Compact non-volatile memory device of the type with charge trapping in a dielectric interface
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Application No.: US16542511Application Date: 2019-08-16
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Publication No.: US10790293B2Publication Date: 2020-09-29
- Inventor: Francesco La Rosa , Stephan Niel , Arnaud Regnier
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee: STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee Address: FR Rousset
- Agency: Slater Matsil, LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@678723a4
- Main IPC: H01L27/11563
- IPC: H01L27/11563 ; H01L21/28 ; H01L27/1157 ; H01L29/423 ; G11C16/04 ; H01L27/11536
Abstract:
A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.
Public/Granted literature
- US20190371805A1 COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING IN A DIELECTRIC INTERFACE Public/Granted day:2019-12-05
Information query
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