Invention Grant
- Patent Title: High performance interconnect physical layer
-
Application No.: US16284742Application Date: 2019-02-25
-
Publication No.: US10795841B2Publication Date: 2020-10-06
- Inventor: Venkatraman Iyer , Darren Jue , Sitaraman Iyer
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06N20/00 ; G06F13/42

Abstract:
A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.
Public/Granted literature
- US20190391945A1 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER Public/Granted day:2019-12-26
Information query