Invention Grant
- Patent Title: Cross-talk generation in a multi-lane link during lane testing
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Application No.: US15990372Application Date: 2018-05-25
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Publication No.: US10853212B2Publication Date: 2020-12-01
- Inventor: Debendra Das Sharma , Daniel S. Froelich
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/22 ; G06F13/42

Abstract:
A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.
Public/Granted literature
- US20190042380A1 CROSS-TALK GENERATION IN A MULTI-LANE LINK DURING LANE TESTING Public/Granted day:2019-02-07
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