Invention Grant
- Patent Title: Methods of lowering wordline resistance
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Application No.: US16000431Application Date: 2018-06-05
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Publication No.: US10854511B2Publication Date: 2020-12-01
- Inventor: Yihong Chen , Yong Wu , Chia Cheng Chin , Xinliang Lu , Srinivas Gandikota , Ziqing Duan , Abhijit Basu Mallick
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Servilla Whitney LLC
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/768 ; H01L21/28 ; H01L21/763 ; H01L27/11556 ; H01L27/11582 ; H01L21/02 ; H01L21/3213 ; H01L21/285 ; G11C8/14
Abstract:
Methods for forming 3D-NAND devices comprising recessing a poly-Si layer to a depth below a spaced oxide layer. A liner is formed on the spaced oxide layer and not on the recessed poly-Si layer. A metal layer is deposited in the gaps on the liner to form wordlines.
Public/Granted literature
- US20180350606A1 Methods Of Lowering Wordline Resistance Public/Granted day:2018-12-06
Information query
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