Invention Grant
- Patent Title: Diffused bitline replacement in stacked wafer memory
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Application No.: US16369631Application Date: 2019-03-29
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Publication No.: US10854578B2Publication Date: 2020-12-01
- Inventor: Stephen Morein
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L25/065 ; H01L29/08 ; H01L23/528 ; H01L29/45 ; H01L21/8234 ; H01L25/00 ; H01L21/02 ; H01L21/768 ; H01L21/321 ; H01L27/105

Abstract:
Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.
Public/Granted literature
- US20200312815A1 DIFFUSED BITLINE REPLACEMENT IN STACKED WAFER MEMORY Public/Granted day:2020-10-01
Information query
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