公开(公告)号：US20200321275A1

公开(公告)日：2020-10-08

申请号：US16837948

申请日：2020-04-01

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Stephen Morein ,  Ilyas Mohammed ,  Rajesh Katkar ,  Javier A. Delacruz

IPC: H01L23/50 ,  H01L23/367 ,  H01L23/49 ,  H01L23/64 ,  H01L21/48

Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.

公开(公告)号：US20200312815A1

公开(公告)日：2020-10-01

申请号：US16369631

申请日：2019-03-29

Applicant: Invensas Corporation

Inventor： Stephen Morein

IPC: H01L25/065 ,  H01L27/105 ,  H01L29/08 ,  H01L23/528 ,  H01L29/45 ,  H01L21/8234 ,  H01L25/00 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L21/321

Abstract: Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

公开(公告)号：US10854578B2

公开(公告)日：2020-12-01

申请号：US16369631

申请日：2019-03-29

Applicant: Invensas Corporation

Inventor： Stephen Morein

IPC: H01L29/66 ,  H01L25/065 ,  H01L29/08 ,  H01L23/528 ,  H01L29/45 ,  H01L21/8234 ,  H01L25/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/321 ,  H01L27/105

Abstract: Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.