- 专利标题： Clock recovery circuits, systems and implementation for increased optical channel density
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申请号： US16270203申请日： 2019-02-07
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公开(公告)号： US10855380B2公开(公告)日： 2020-12-01
- 发明人: Sadok Aouini , Bilal Riaz , Naim Ben-Hamida , Lukas Jakober , Ahmad Abdo
- 申请人： Ciena Corporation
- 申请人地址： US MD Hanover
- 专利权人： Ciena Corporation
- 当前专利权人： Ciena Corporation
- 当前专利权人地址： US MD Hanover
- 代理机构： Clements Bernard Walker
- 代理商 Lawrence A. Baratta, Jr.; Christopher L. Bernard
- 主分类号： H04B10/61
- IPC分类号： H04B10/61 ; H04B10/572 ; H04B10/60 ; H03L7/23 ; H04L7/033 ; H03L7/099 ; H04B10/69 ; H04L7/00 ; H03L7/087 ; H03L7/093 ; H03L7/081
摘要：
Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.
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