公开(公告)号：US12107596B2

公开(公告)日：2024-10-01

申请号：US17961845

申请日：2022-10-07

申请人： Ciena Corporation

发明人： Mouna Safi-Harab ,  Soheyl Ziabakhsh Shalmani ,  Sadok Aouini ,  Naim Ben-Hamida

IPC分类号： H03M1/10 ,  H03M1/16 ,  H03M1/46 ,  H03M1/50

CPC分类号： H03M1/462 ,  H03M1/16 ,  H03M1/504

摘要： A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.

公开(公告)号：US20220385365A1

公开(公告)日：2022-12-01

申请号：US17329335

申请日：2021-05-25

申请人： Ciena Corporation

发明人： Sadok Aouini ,  Robert G. Gibbins ,  Yalmez Yazaw ,  Harvey Mah ,  Naim Ben-Hamida

IPC分类号： H04B10/2513 ,  H04B10/2569

摘要： An optical Digital Signal Processor (DSP) circuit includes a digital core configured to implement digital signal processing functionality and configured to operate at a plurality of baud rates including a full baud rate and a half-baud rate; and an analog interface including a Digital-to-Analog Converter (DAC) section and an Analog-to-Digital Converter (ADC) section, wherein the analog interface is connected to the digital core and is configured to operate at the full baud rate when the digital core is configured to operate at any of the plurality of baud rates.

公开(公告)号：US11218155B2

公开(公告)日：2022-01-04

申请号：US17101665

申请日：2020-11-23

申请人： Ciena Corporation

发明人： Tingjun Wen ,  Sadok Aouini ,  Naim Ben-Hamida ,  Mahdi Parvizi ,  Matthew Mikkelsen

IPC分类号： H03L7/06 ,  H03L7/197 ,  H03L7/087 ,  H03L7/107 ,  H03L7/093 ,  H03L7/099

摘要： Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.

公开(公告)号：US10855380B2

公开(公告)日：2020-12-01

申请号：US16270203

申请日：2019-02-07

申请人： Ciena Corporation

发明人： Sadok Aouini ,  Bilal Riaz ,  Naim Ben-Hamida ,  Lukas Jakober ,  Ahmad Abdo

IPC分类号： H04B10/61 ,  H04B10/572 ,  H04B10/60 ,  H03L7/23 ,  H04L7/033 ,  H03L7/099 ,  H04B10/69 ,  H04L7/00 ,  H03L7/087 ,  H03L7/093 ,  H03L7/081

摘要： Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.

公开(公告)号：US10805064B1

公开(公告)日：2020-10-13

申请号：US16391527

申请日：2019-04-23

申请人： Ciena Corporation

发明人： Sadok Aouini ,  Naim Ben-Hamida ,  Ahmad Abdo ,  Timothy James Creasy ,  Lukas Jakober ,  Yalmez M. A. Yazaw ,  Shahab Oveis Gharan

IPC分类号： H04B10/50 ,  H04B10/69 ,  H04L7/033 ,  H04B10/071 ,  H04B10/40 ,  H04B10/25 ,  H04B10/079

摘要： A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).

公开(公告)号：US10715155B1

公开(公告)日：2020-07-14

申请号：US16600808

申请日：2019-10-14

申请人： Ciena Corporation

发明人： Mahdi Parvizi ,  Sadok Aouini ,  Naim Ben-Hamida

IPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/089

摘要： Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.

公开(公告)号：US10680585B2

公开(公告)日：2020-06-09

申请号：US15947924

申请日：2018-04-09

申请人： Ciena Corporation

发明人： Sadok Aouini ,  Naim Ben-Hamida ,  Mahdi Parvizi

IPC分类号： H03K3/013 ,  H03L7/083 ,  G01R29/26 ,  G01R31/317 ,  H03L7/099

摘要： Digital jitter accumulation reduction techniques and circuits are proposed to mitigate jitter accumulation in Voltage Controlled Oscillators (VCOs). In order to reduce jitter accumulation, employing a pair of identical injection locked VCOs is proposed in an interleaved fashion. Further jitter accumulation reductions can be provided by employing a plurality of identical injection locked VCOs selected in a cascading fashion. Yet further jitter accumulation reductions can be provided by resetting the deselected VCO(s).

公开(公告)号：US20200081314A1

公开(公告)日：2020-03-12

申请号：US16126061

申请日：2018-09-10

申请人： Ciena Corporation

发明人： Mahdi Parvizi ,  Naim Ben-Hamida

IPC分类号： G02F1/225

摘要： Disclosed herein are architectures for low power, low voltage traveling wave Mach-Zehnder optical modulators. By combining single-ended series push-pull modulator configurations with differential dual-drive modulator configurations, the advantages of each type may be utilized. In particular, the halved capacitance of single-ended series push-pull modulators may reduce microwave losses, thereby improving bandwidth performance within modulator configurations. Moreover, reduced required drive voltage of dual-drive modulators coupled with increased impedance may advantageously minimize the power consumption and maximize efficiency in the differential traveling wave series push-pull Mach-Zehnder modulator configurations disclosed herein.

公开(公告)号：US20190190617A1

公开(公告)日：2019-06-20

申请号：US16270203

申请日：2019-02-07

申请人： Ciena Corporation

发明人： Sadok Aouini ,  Bilal Riaz ,  Naim Ben-Hamida ,  Lukas Jakober ,  Ahmad Abdo

IPC分类号： H04B10/61 ,  H04B10/572

CPC分类号： H04B10/6165 ,  H03L7/081 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H03L7/235 ,  H03L2207/06 ,  H04B10/572 ,  H04B10/60 ,  H04B10/6163 ,  H04B10/6164 ,  H04B10/697 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0335

摘要： Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.

公开(公告)号：US10187197B2

公开(公告)日：2019-01-22

申请号：US16042425

申请日：2018-07-23

申请人： Ciena Corporation

发明人： Sadok Aouini ,  Naim Ben-Hamida ,  Christopher Kurowski ,  Lukas Jakober

IPC分类号： H03L7/00 ,  H03L7/06 ,  H03L7/08 ,  H04B10/40 ,  H04L7/033 ,  H04L25/49 ,  H03D3/24

摘要： A method for clock recovery that may include obtaining an output signal from a phase locked loop (PLL) device. The method may further include determining, using a digital phase detector, the output signal, and a transmitter clock signal, an amount of phase difference between the output signal and the transmitter clock signal. The method may further include filtering, using a phase rotator and a digital accumulator, a portion of the amount of phase difference from the output signal to generate a filtered signal.