Invention Grant
- Patent Title: Patterning approach for improved via landing profile
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Application No.: US16229818Application Date: 2018-12-21
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Publication No.: US10861788B2Publication Date: 2020-12-08
- Inventor: Chih-Yuan Ting , Chung-Wen Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/522 ; H01L21/768 ; H01L23/532

Abstract:
The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.
Public/Granted literature
- US20190148294A1 NOVEL PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE Public/Granted day:2019-05-16
Information query
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