Patterning approach for improved via landing profile

    公开(公告)号:US10861788B2

    公开(公告)日:2020-12-08

    申请号:US16229818

    申请日:2018-12-21

    Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

    Novel Patterning Approach for Improved Via Landing Profile
    4.
    发明申请
    Novel Patterning Approach for Improved Via Landing Profile 有权
    改进通道着陆轮廓的新型图案化方法

    公开(公告)号:US20140264902A1

    公开(公告)日:2014-09-18

    申请号:US13794999

    申请日:2013-03-12

    Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

    Abstract translation: 本公开涉及一种半导体结构及其制造方法,其中间隔元件邻近嵌入在第一互连层的第一电介质层中的金属体形成。 相对于金属体的边缘不对准的通孔形成在第二互连层中的第二介电材料中,第二互连层设置在第一互连层上并且填充有电耦合到金属体的导电材料。 该方法允许形成互连结构,而不会遇到通过第一互连层的电介质材料中的子结构缺陷所呈现的各种问题,以及消除常规间隙填充金属化问题。

    Method and Apparatus for Back End of Line Semiconductor Device Processing

    公开(公告)号:US20220359274A1

    公开(公告)日:2022-11-10

    申请号:US17869177

    申请日:2022-07-20

    Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

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