公开(公告)号：US11980040B2

公开(公告)日：2024-05-07

申请号：US17346855

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Tsung-Hsien Chang ,  Yu-Shu Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  G11C11/16

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  G11C11/1659

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

公开(公告)号：US20210313396A1

公开(公告)日：2021-10-07

申请号：US17346855

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Tsung-Hsien Chang ,  Yu-Shu Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

公开(公告)号：US10861788B2

公开(公告)日：2020-12-08

申请号：US16229818

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

公开(公告)号：US20140264902A1

公开(公告)日：2014-09-18

申请号：US13794999

申请日：2013-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract translation: 本公开涉及一种半导体结构及其制造方法，其中间隔元件邻近嵌入在第一互连层的第一电介质层中的金属体形成。 相对于金属体的边缘不对准的通孔形成在第二互连层中的第二介电材料中，第二互连层设置在第一互连层上并且填充有电耦合到金属体的导电材料。 该方法允许形成互连结构，而不会遇到通过第一互连层的电介质材料中的子结构缺陷所呈现的各种问题，以及消除常规间隙填充金属化问题。

公开(公告)号：US11800812B2

公开(公告)日：2023-10-24

申请号：US17688370

申请日：2022-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Chien-Chung Huang ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Hui-Hsien Wei

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/10 ,  H10B61/22 ,  H10B61/00 ,  H10N50/80

Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.

公开(公告)号：US11665971B2

公开(公告)日：2023-05-30

申请号：US17408648

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Yu-Shu Chen ,  Chien Chung Huang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Chih-Yuan Ting

IPC: H01L21/00 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02

Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

公开(公告)号：US20220359274A1

公开(公告)日：2022-11-10

申请号：US17869177

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wen Wu ,  Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/762 ,  H01L23/48 ,  H01L51/00

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

公开(公告)号：US20180174853A1

公开(公告)日：2018-06-21

申请号：US15474522

申请日：2017-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/308 ,  H01L21/265 ,  H01L21/027

CPC classification number: H01L21/26586 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.

公开(公告)号：US09640435B2

公开(公告)日：2017-05-02

申请号：US15088292

申请日：2016-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

公开(公告)号：US20240251568A1

公开(公告)日：2024-07-25

申请号：US18626670

申请日：2024-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Tsung-Hsien Chang ,  Yu-Shu Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/10

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  G11C11/1659

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.