Invention Grant
- Patent Title: Offset addition circuits for sense transistors
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Application No.: US16105604Application Date: 2018-08-20
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Publication No.: US10862443B2Publication Date: 2020-12-08
- Inventor: Nandakishore Raimar
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R19/00
- IPC: G01R19/00 ; G01R19/15 ; H03F3/45 ; H03G3/30 ; G01R15/00 ; H02P6/28

Abstract:
In examples, an apparatus for sensing current comprises a power transistor; a sense transistor coupled to the power transistor; and an offset addition circuit coupled to the power transistor and the sense transistor, the offset addition circuit comprising a first pair of transistors and a differential amplifier. The apparatus also comprises a cascode amplifier circuit coupled to the offset addition circuit, the cascode amplifier circuit comprising a second pair of transistors, and a gain trim circuit coupled to the cascode amplifier circuit, the gain trim circuit including another differential amplifier and a third transistor. The apparatus further includes an analog-to-digital converter (ADC) coupled to the gain trim circuit and storage coupled to the ADC.
Public/Granted literature
- US20200059212A1 OFFSET ADDITION CIRCUITS FOR SENSE TRANSISTORS Public/Granted day:2020-02-20
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