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公开(公告)号：US20160299520A1
公开(公告)日：2016-10-13
申请号：US14685590
申请日：2015-04-13
Applicant: Texas Instruments Incorporated
Inventor： Prasadu Mangina , Biranchinath Sahu , Pradeep Pydah , Nandakishore Raimar
IPC: G05F1/575
Abstract: Undershoot reduction circuitry includes, for example, a first comparator, a second comparator, and a controller. The first comparator is operable for comparing an indication of a power supply voltage output against a first threshold. The second comparator is operable for comparing an indication of the power supply voltage output against a second threshold. The controller is operable for generating a first power control signal to raise the power supply voltage output when the indication of the power supply voltage output has a first slope and crosses the first threshold and to lower the power supply voltage output when the indication of the power supply voltage output has an opposite slope and crosses the second threshold.
Abstract translation: 下冲还原电路包括例如第一比较器，第二比较器和控制器。 第一比较器可操作用于将电源电压输出的指示与第一阈值进行比较。 第二比较器可操作用于将电源电压输出的指示与第二阈值进行比较。 当电源电压输出的指示具有第一斜率并且跨越第一阈值并且当电力指示时降低电源电压输出时，控制器可操作用于产生第一功率控制信号以提高电源电压输出 电源电压输出具有相反的斜率并跨越第二阈值。
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Patent Agency Ranking
公开(公告)号：US20180309362A1
公开(公告)日：2018-10-25
申请号：US15495966
申请日：2017-04-24
Applicant: Texas Instruments Incorporated
Inventor： Nandakishore Raimar , Sayantan Gupta
IPC: H02M3/07
CPC classification number: H02M3/07 , H02M3/073 , H02M2001/0006 , H02M2003/075
Abstract: A VBOOST generator includes, for example, a voltage regulator for generating a first power rail VX between the supply voltage VCC and ground. A clock generator is arranged to generate a clock signal oscillating between the supply voltage VCC and the voltage VCC−VX. A charge pump is arranged to couple the voltage VCC−VX to a first terminal of an on-substrate flyback capacitor during a first half-cycle of the first clock signal and is arranged to couple the voltage VCC to the first terminal of the flyback capacitor during a second half-cycle of the first clock signal. A pin is coupled to the substrate couples the voltage VCC+VX developed on a second terminal of the flyback capacitor during the second half-cycle of the first clock signal to an external bucket capacitor. A second charge pump is optionally included to increase the charging capacity of the VBOOST generator.
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公开(公告)号：US10447153B2
公开(公告)日：2019-10-15
申请号：US15495966
申请日：2017-04-24
Applicant: Texas Instruments Incorporated
Inventor： Nandakishore Raimar , Sayantan Gupta
Abstract: A VBOOST generator includes, for example, a voltage regulator for generating a first power rail VX between the supply voltage VCC and ground. A clock generator is arranged to generate a clock signal oscillating between the supply voltage VCC and the voltage VCC−VX. A charge pump is arranged to couple the voltage VCC−VX to a first terminal of an on-substrate flyback capacitor during a first half-cycle of the first clock signal and is arranged to couple the voltage VCC to the first terminal of the flyback capacitor during a second half-cycle of the first clock signal. A pin is coupled to the substrate couples the voltage VCC+VX developed on a second terminal of the flyback capacitor during the second half-cycle of the first clock signal to an external bucket capacitor. A second charge pump is optionally included to increase the charging capacity of the VBOOST generator.
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公开(公告)号：US10084307B2
公开(公告)日：2018-09-25
申请号：US15141365
申请日：2016-04-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Pradeep V S R Pydah , Biranchinath Sahu , Tetsuo Tateishi , Kuang-Yao Cheng , Nandakishore Raimar
CPC classification number: H02H7/1213 , G06F1/26 , G06F1/28 , G06F1/305 , H02H3/087
Abstract: The disclosure provides an over-current protection circuit. A signal generating block in the over-current protection circuit generates one or more input voltages, a summed voltage and an average voltage in response to one or more differential voltages. A control block generates one or more control signals in response to the one or more input voltages and the average voltage. An analog control loop block generates an initiation signal in response to the summed voltage and an output voltage. A phase control logic block generates one or more PWM (pulse width modulated) signals in response to the initiation signal and the one or more control signals.
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公开(公告)号：US09817414B2
公开(公告)日：2017-11-14
申请号：US14685590
申请日：2015-04-13
Applicant: Texas Instruments Incorporated
Inventor： Naga Venkata Prasadu Mangina , Biranchinath Sahu , Pradeep V S R Pydah , Nandakishore Raimar
Abstract: Undershoot reduction circuitry includes, for example, a first comparator, a second comparator, and a controller. The first comparator is operable for comparing an indication of a power supply voltage output against a first threshold. The second comparator is operable for comparing an indication of the power supply voltage output against a second threshold. The controller is operable for generating a first power control signal to raise the power supply voltage output when the indication of the power supply voltage output has a first slope and crosses the first threshold and to lower the power supply voltage output when the indication of the power supply voltage output has an opposite slope and crosses the second threshold.
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公开(公告)号：US10862443B2
公开(公告)日：2020-12-08
申请号：US16105604
申请日：2018-08-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nandakishore Raimar
Abstract: In examples, an apparatus for sensing current comprises a power transistor; a sense transistor coupled to the power transistor; and an offset addition circuit coupled to the power transistor and the sense transistor, the offset addition circuit comprising a first pair of transistors and a differential amplifier. The apparatus also comprises a cascode amplifier circuit coupled to the offset addition circuit, the cascode amplifier circuit comprising a second pair of transistors, and a gain trim circuit coupled to the cascode amplifier circuit, the gain trim circuit including another differential amplifier and a third transistor. The apparatus further includes an analog-to-digital converter (ADC) coupled to the gain trim circuit and storage coupled to the ADC.
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