A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.