Invention Grant
- Patent Title: Technologies for balancing throughput across input ports of a multi-stage network switch
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Application No.: US15639816Application Date: 2017-06-30
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Publication No.: US10911366B2Publication Date: 2021-02-02
- Inventor: Scott S. Diesing , Michael A. Parker , Albert S. Cheng , Nan Ni
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: H04L12/54
- IPC: H04L12/54 ; H04L12/70 ; H04L12/773 ; H04L12/803 ; H04L12/863 ; H04L12/867 ; H04L12/869 ; H04L12/933 ; H04L12/935

Abstract:
Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.
Public/Granted literature
- US20190007319A1 TECHNOLOGIES FOR BALANCING THROUGHPUT ACROSS INPUT PORTS OF A MULTI-STAGE NETWORK SWITCH Public/Granted day:2019-01-03
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