- 专利标题： Peripheral component interconnect express (PCIE) network with input/output (I/O) operation chaining to reduce communication time within execution of I/O channel operations
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申请号： US16682481申请日： 2019-11-13
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公开(公告)号： US10949097B2公开(公告)日： 2021-03-16
- 发明人: Edward W. Chencinski , Bruce Ratcliff , Eric N. Lais , Michael James Becht , Matthias Klein
- 申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 代理机构： Heslin Rothenberg Farley & Mesiti P.C.
- 代理商 Steven Chiu, Esq.; Blanche E. Schiller, Esq.
- 主分类号： G06F3/06
- IPC分类号： G06F3/06 ; G06F13/16 ; G06F13/42
摘要：
A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.
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