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    Packet flow tracing in a parallel processor complex
    1.
    发明授权
    Packet flow tracing in a parallel processor complex 有权

    公开(公告)号：US11086748B2

    公开(公告)日：2021-08-10

    申请号：US16438581

    申请日：2019-06-12

    申请人： International Business Machines Corporation

    发明人： Bruce Ratcliff

    IPC分类号： G06F9/46 ,  G06F11/34 ,  G06F11/30 ,  G06F9/28 ,  G06F11/36 ,  G06F15/80 ,  H04L12/26

    摘要： In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

    PACKET FLOW TRACING IN A PARALLEL PROCESSOR COMPLEX
    5.
    发明申请
    PACKET FLOW TRACING IN A PARALLEL PROCESSOR COMPLEX 审中-公开

    公开(公告)号：US20190294521A1

    公开(公告)日：2019-09-26

    申请号：US16438589

    申请日：2019-06-12

    申请人： International Business Machines Corporation

    发明人： Bruce Ratcliff

    IPC分类号： G06F11/34 ,  G06F11/36 ,  G06F11/30 ,  H04L12/26 ,  G06F15/80 ,  G06F9/28

    摘要： In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.

    Selectively refreshing address registration information
    7.
    发明授权
    Selectively refreshing address registration information 有权
    选择性刷新地址注册信息

    公开(公告)号：US09419879B2

    公开(公告)日：2016-08-16

    申请号：US13922300

    申请日：2013-06-20

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Jeffrey D. Haggar ,  Bruce Ratcliff ,  Benjamin T. Rau ,  Jerry W. Stevens

    IPC分类号： H04L12/28 ,  H04L12/26 ,  H04L29/12 ,  G06F9/455

    CPC分类号： H04L61/2076 ,  G06F9/45558 ,  G06F2009/45595 ,  H04L43/08 ,  H04L43/0876 ,  H04L45/72 ,  H04L45/745 ,  H04L49/25 ,  H04L61/10 ,  H04L61/103 ,  H04L61/2038 ,  H04L61/6022

    摘要： Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.

    摘要翻译： 促进处理环境中的通信。 监视处理环境的一个或多个虚拟接口上的入站流量和出站流量预定义的时间量。 基于该监视，确定对于一个或多个虚拟接口的虚拟接口的选定组件是否已经接收到入站帧，但是是否在预定时间量内尚未发送出站帧。 基于确定已经接收到入站帧而没有发送出站帧，转发所生成的出站帧，以引起要刷新的虚拟接口的地址注册信息。

    Packet flow tracing in a parallel processor complex
    9.
    发明授权
    Packet flow tracing in a parallel processor complex 有权

    公开(公告)号：US10417109B2

    公开(公告)日：2019-09-17

    申请号：US15441408

    申请日：2017-02-24

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bruce Ratcliff

    IPC分类号： G06F9/46 ,  G06F11/34 ,  G06F11/30 ,  G06F9/28 ,  G06F11/36 ,  G06F15/80 ,  H04L12/26

    摘要： Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.