- 专利标题: Bimodal PHY for low latency in high speed interconnects
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申请号: US16802209申请日: 2020-02-26
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公开(公告)号: US10963415B2公开(公告)日: 2021-03-30
- 发明人: Venkatraman Iyer , William R. Halleck , Rahul R. Shah , Eric Lee
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Trop, Pruner & Hu, P.C.
- 主分类号: G06F13/40
- IPC分类号: G06F13/40 ; G06F13/38 ; G06F13/42 ; G06F13/16
摘要:
Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.
公开/授权文献
- US20200293480A1 BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 公开/授权日:2020-09-17