公开(公告)号：US20190310959A1

公开(公告)日：2019-10-10

申请号：US16446996

申请日：2019-06-20

申请人： INTEL CORPORATION

发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/16 ,  G06F13/42

摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

公开(公告)号：US10372657B2

公开(公告)日：2019-08-06

申请号：US15390648

申请日：2016-12-26

申请人： Intel Corporation

发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC分类号： G06F13/00 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The low pin count PIPE interface is configured to transfer register commands between the PHY and MAC blocks over the small set of wires in a time-multiplexed manner to support read and write access of the PHY and MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture when operating in a PIPE mode and a serialization and deserialization (SERDES) architecture when operating in a SERDES mode.

公开(公告)号：US10599602B2

公开(公告)日：2020-03-24

申请号：US16446996

申请日：2019-06-20

申请人： INTEL CORPORATION

发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

公开(公告)号：US20180181525A1

公开(公告)日：2018-06-28

申请号：US15390648

申请日：2016-12-26

申请人： Intel Corporation

发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC分类号： G06F13/4068 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/382 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0026

摘要： Systems, methods, and apparatuses involve a PHY coupled to a MAC. The PHY can include a drift buffer coupled to an output of a receiver and a bypass branch coupled to the output of the receiver. The PHY includes a clocking multiplexer that includes a first clock input coupled to a recovered clock of the PHY and a second clock input coupled to a p-clock of the MAC; and a clock output configured to output one of the recovered clock or the p-clock based on a selection input value. The PHY includes a bypass multiplexer that includes a first data input coupled to an output of a drift buffer and a second data input coupled to the bypass branch; and a data output configured to output one of the output of the drift buffer or data from the bypass branch based on the section input value of the clocking multiplexer.

公开(公告)号：US11354264B2

公开(公告)日：2022-06-07

申请号：US17184737

申请日：2021-02-25

申请人： Intel Corporation

发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

公开(公告)号：US20210182231A1

公开(公告)日：2021-06-17

申请号：US17184737

申请日：2021-02-25

申请人： Intel Corporation

发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

公开(公告)号：US10963415B2

公开(公告)日：2021-03-30

申请号：US16802209

申请日：2020-02-26

申请人： INTEL CORPORATION

发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

公开(公告)号：US20200293480A1

公开(公告)日：2020-09-17

申请号：US16802209

申请日：2020-02-26

申请人： INTEL CORPORATION

发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.