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    Bimodal phy for low latency in high speed interconnects
    2.
    发明授权
    Bimodal phy for low latency in high speed interconnects 有权

    公开(公告)号：US10599602B2

    公开(公告)日：2020-03-24

    申请号：US16446996

    申请日：2019-06-20

    申请人： INTEL CORPORATION

    发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

    摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    3.
    发明申请
    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 审中-公开

    公开(公告)号：US20180181525A1

    公开(公告)日：2018-06-28

    申请号：US15390648

    申请日：2016-12-26

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/16

    CPC分类号： G06F13/4068 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/382 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0026

    摘要： Systems, methods, and apparatuses involve a PHY coupled to a MAC. The PHY can include a drift buffer coupled to an output of a receiver and a bypass branch coupled to the output of the receiver. The PHY includes a clocking multiplexer that includes a first clock input coupled to a recovered clock of the PHY and a second clock input coupled to a p-clock of the MAC; and a clock output configured to output one of the recovered clock or the p-clock based on a selection input value. The PHY includes a bypass multiplexer that includes a first data input coupled to an output of a drift buffer and a second data input coupled to the bypass branch; and a data output configured to output one of the output of the drift buffer or data from the bypass branch based on the section input value of the clocking multiplexer.

    LINK-PHYSICAL LAYER INTERFACE ADAPTER
    4.
    发明申请
    LINK-PHYSICAL LAYER INTERFACE ADAPTER 审中-公开

    公开(公告)号：US20180095923A1

    公开(公告)日：2018-04-05

    申请号：US15283309

    申请日：2016-10-01

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  Mahesh Wagh ,  William R. Halleck ,  Rahul R. Shah

    IPC分类号： G06F13/40 ,  G06F13/36 ,  G06F13/42

    CPC分类号： G06F13/4068 ,  G06F13/36 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4265 ,  G11C27/04

    摘要： An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.

    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    5.
    发明申请
    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 有权

    公开(公告)号：US20210182231A1

    公开(公告)日：2021-06-17

    申请号：US17184737

    申请日：2021-02-25

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

    摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    Bimodal PHY for low latency in high speed interconnects
    6.
    发明授权
    Bimodal PHY for low latency in high speed interconnects 有权

    公开(公告)号：US10963415B2

    公开(公告)日：2021-03-30

    申请号：US16802209

    申请日：2020-02-26

    申请人： INTEL CORPORATION

    发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

    摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    High speed interconnect with channel extension
    7.
    发明授权
    High speed interconnect with channel extension 有权

    公开(公告)号：US10931329B2

    公开(公告)日：2021-02-23

    申请号：US15394278

    申请日：2016-12-29

    申请人： Intel Corporation

    发明人： Rahul R. Shah ,  William R. Halleck ,  Fulvio Spagna ,  Venkatraman Iyer

    IPC分类号： H04L12/407 ,  H04B3/36 ,  H04L12/933 ,  H04L12/803 ,  G06F13/40

    摘要： An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.

    HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS
    10.
    发明申请
    HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS 审中-公开

    公开(公告)号：US20170109300A1

    公开(公告)日：2017-04-20

    申请号：US15393631

    申请日：2016-12-29

    申请人： Intel Corporation

    发明人： William R. Halleck ,  Rahul R. Shah ,  Venkatraman Iyer

    IPC分类号： G06F13/16 ,  G06F13/12

    CPC分类号： G06F13/4027 ,  G06F13/124 ,  G06F13/1678 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

    摘要： An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.