Invention Grant
- Patent Title: Adaptive VPASS for 3D flash memory with pair string structure
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Application No.: US16912720Application Date: 2020-06-26
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Publication No.: US10971231B1Publication Date: 2021-04-06
- Inventor: Rajdeep Gautam , Hardwell Chibvongodze , Ken Oowada
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/34 ; G11C11/56 ; G11C16/10 ; G11C16/28

Abstract:
Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.
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