公开(公告)号：US11361816B2

公开(公告)日：2022-06-14

申请号：US16996412

申请日：2020-08-18

Applicant: SanDisk Technologies LLC

Inventor： Zhixin Cui ,  Rajdeep Gautam ,  Hardwell Chibvongodze

IPC: G11C11/4094 ,  G11C11/4093 ,  G11C5/02 ,  G11C11/408 ,  G11C11/4074

Abstract: Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform program and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with an insulating material. Contacts to the source regions can include post-shaped contacts which extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, a program operation applies different voltages to the respective source regions during a verify test of a program operation.

公开(公告)号：US11222954B2

公开(公告)日：2022-01-11

申请号：US16828129

申请日：2020-03-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Hardwell Chibvongodze ,  Masatoshi Nishikawa

IPC: G11C11/34 ,  H01L29/423 ,  H01L27/11582 ,  H01L29/417 ,  H01L21/28 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.

公开(公告)号：US10734080B2

公开(公告)日：2020-08-04

申请号：US16213382

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: G11C16/24 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  H01L27/11526 ,  G11C16/14 ,  G11C16/10

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US20200185039A1

公开(公告)日：2020-06-11

申请号：US16213382

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: G11C16/24 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US20240364338A1

公开(公告)日：2024-10-31

申请号：US18346344

申请日：2023-07-03

Applicant: SanDisk Technologies LLC

Inventor： Alvin Joshua ,  Hardwell Chibvongodze ,  Yuki Kuniyoshi ,  Akitomo Nakayama

IPC: H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/356113

Abstract: On memory die and other circuits, some parts may operate at a VDD logic level while other elements operate at a higher logic level, such as at or near the die's supply level VSUP. To reduce power consumption and increase operating speeds, VDD levels are moving to increasingly lower voltages. To raise the logic signal from the lower level to the higher, level shifters can be used. However, as the gap between the supply level VSUP and VDD widens, it can become difficult for a level shifter to reliably raise a logic signal operating at the VDD level to the VSUP level. The address this problem, the following introduces a small charge pump to boost the input logic signals for level shifter circuits to allow them to reliably generate an output logic signal at the VSUP level from an input logic signal at low VDD levels.

公开(公告)号：US20220059157A1

公开(公告)日：2022-02-24

申请号：US16996412

申请日：2020-08-18

Applicant: SanDisk Technologies LLC

Inventor： Zhixin Cui ,  Rajdeep Gautam ,  Hardwell Chibvongodze

IPC: G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/408 ,  G11C5/02

Abstract: Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform program and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with an insulating material. Contacts to the source regions can include post-shaped contacts which extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, a program operation applies different voltages to the respective source regions during a verify test of a program operation,

公开(公告)号：US11024385B2

公开(公告)日：2021-06-01

申请号：US16415377

申请日：2019-05-17

Applicant: SanDisk Technologies LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa

IPC: G11C11/34 ,  G11C16/10 ,  G11C7/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/34

Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.

公开(公告)号：US10978152B1

公开(公告)日：2021-04-13

申请号：US16682730

申请日：2019-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C11/56 ,  G11C16/34

Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.

公开(公告)号：US20200185397A1

公开(公告)日：2020-06-11

申请号：US16213180

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: H01L27/11548 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US11487454B2

公开(公告)日：2022-11-01

申请号：US16704729

申请日：2019-12-05

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze

IPC: G11C16/24 ,  G06F3/06 ,  G06F13/16 ,  G11C16/14 ,  G11C16/04

Abstract: A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.