Invention Grant
- Patent Title: Method for contacting a buried interconnect rail of an integrated circuit chip from the back side of the IC
-
Application No.: US16675080Application Date: 2019-11-05
-
Publication No.: US10985057B2Publication Date: 2021-04-20
- Inventor: Anne Jourdain , Nouredine Rassoul , Eric Beyne
- Applicant: IMEC vzw
- Applicant Address: BE Leuven
- Assignee: IMEC vzw
- Current Assignee: IMEC vzw
- Current Assignee Address: BE Leuven
- Agency: Knobbe Martens Olson & Bear LLP
- Priority: EP18205606 20181112
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/308 ; H01L21/321 ; H01L21/463 ; H01L21/48 ; H01L23/538

Abstract:
A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.
Public/Granted literature
Information query
IPC分类: