公开(公告)号：US20220020882A1

公开(公告)日：2022-01-20

申请号：US17305797

申请日：2021-07-14

Applicant: IMEC vzw

Inventor： Nouredine Rassoul ,  Romain Delhougne ,  Attilio Belmonte ,  Gouri Sankar Kar

IPC: H01L29/786 ,  H01L29/66 ,  H01L23/00 ,  H01L29/24 ,  H01L29/10

Abstract: The disclosed technology generally relates to a structure for a field effect transistor (FET) device and a method of processing a FET device. In one aspect, the method can include providing a substrate, forming an oxygen passing layer on the substrate, and forming an oxygen blocking layer on the substrate. The oxygen blocking layer can be arranged next to the oxygen passing layer and can delimit the oxygen passing layer on two opposite sides. The method can also include forming an oxide semiconductor layer on the oxygen passing layer and the oxygen blocking layer, forming a gate structure on the oxide semiconductor layer in a region above the oxygen passing layer, and modifying a doping of the oxide semiconductor layer by introducing oxygen into the oxygen passing layer. At least a portion of the introduced oxygen can pass through the oxygen passing layer and into the oxide semiconductor layer.

公开(公告)号：US20240107739A1

公开(公告)日：2024-03-28

申请号：US18472122

申请日：2023-09-21

Applicant: IMEC VZW

Inventor： Nouredine Rassoul ,  Hyungrock Oh ,  Romain Delhougne ,  Gouri Sankar Kar ,  Attilio Belmonte ,  Kaustuv Banerjee ,  Mohit Gupta

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A memory device configured as a dynamic random access memory is provided, comprising a first semiconductor device layer comprising a first bit cell and a second semiconductor device layer comprising a second DRAM bit cell. Further, at least one of a first and second interconnecting structure is provided, the first interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a write word line common to the gate terminal of the write transistors of the first and second bit cells, and the second interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a read word line common to a first source/drain terminal of the read transistors of the first and second bit cells.

公开(公告)号：US20200152508A1

公开(公告)日：2020-05-14

申请号：US16675080

申请日：2019-11-05

Applicant: IMEC vzw

Inventor： Anne Jourdain ,  Nouredine Rassoul ,  Eric Beyne

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/463 ,  H01L21/48 ,  H01L21/308

Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.

公开(公告)号：US20220209022A1

公开(公告)日：2022-06-30

申请号：US17646072

申请日：2021-12-27

Applicant: IMEC vzw

Inventor： Nouredine Rassoul ,  Gabriele Luca Donadio ,  Gouri Sankar Kar

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/477

Abstract: The disclosed technology generally relates to a method of processing a field effect transistor (FET) device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a thin-film-transistor (TFT). In one aspect, the method includes providing a substrate; forming a first oxide semiconductor layer and a second oxide semiconductor layer above the substrate; forming a source structure and a drain structure on the second oxide semiconductor layer; and forming a gate structure on the first oxide semiconductor layer. The first oxide semiconductor layer forms a channel between the source structure and the drain structure. The second oxide semiconductor layer forms a contact layer to the source structure and the drain structure.

公开(公告)号：US10985057B2

公开(公告)日：2021-04-20

申请号：US16675080

申请日：2019-11-05

Applicant: IMEC vzw

Inventor： Anne Jourdain ,  Nouredine Rassoul ,  Eric Beyne

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/321 ,  H01L21/463 ,  H01L21/48 ,  H01L23/538

Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.