公开(公告)号：US20230142597A1

公开(公告)日：2023-05-11

申请号：US18048005

申请日：2022-10-19

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Eric Beyne ,  Anne Jourdain

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L21/76877 ,  H01L21/78 ,  H01L21/76802 ,  H01L22/12

Abstract: A method of producing an IC chip is provided. In one aspect, deep trenches are formed in a semiconductor layer that forms the top layer of a device wafer, the trenches going through the complete thickness of the layer. The trenches are filled with a sacrificial material, that is etched back and covered with a capping layer, thereby forming sacrificial buried rails. After processing active devices on the front surface of the semiconductor layer, including connections to the sacrificial rails, the device wafer is bonded face down to a carrier wafer, and thinned from the back side, until the sacrificial rails are exposed. The sacrificial material and the capping layer are removed and replaced by a conductive material, thereby forming the actual buried power rails. A back side power delivery network supplies power through the buried rails to the active devices of the IC. Using a sacrificial material for the buried rails can enable a wider choice of materials for these buried rails.

公开(公告)号：US20220270924A1

公开(公告)日：2022-08-25

申请号：US17669255

申请日：2022-02-10

Applicant: IMEC VZW

Inventor： Douglas Charles La Tulipe ,  Anne Jourdain ,  Gaspard Hiblot

IPC: H01L21/768 ,  H01L23/544

Abstract: The disclosed technology relates to methods for producing an interconnect structure on the back side of an integrated circuit chip. According to a first aspect, a via opening is etched in a top semiconductor layer, and filled with a sacrificial material, thereby forming a sacrificial pillar. Then front and back end of line portions are processed and the substrate is thinned. The etch stop layer and the sacrificial pillar are removed, and replaced an electrically conductive material forming a through semiconductor via. According to a second aspect, the sacrificial pillar is etched through the opening of a trench that intersects the pillar. Filling the trench with a conductive material also fills the cavity created by etching back the pillar resulting in an integral conductive pad and interconnect rail structure. The pillar can be removed and replaced by a conductive material, thereby creating the TSV connection.

公开(公告)号：US20230080522A1

公开(公告)日：2023-03-16

申请号：US17932582

申请日：2022-09-15

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Anne Jourdain ,  Anabela Veloso

IPC: H01L23/528 ,  H01L23/522

Abstract: An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices on its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.

公开(公告)号：US20200152508A1

公开(公告)日：2020-05-14

申请号：US16675080

申请日：2019-11-05

Applicant: IMEC vzw

Inventor： Anne Jourdain ,  Nouredine Rassoul ,  Eric Beyne

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/463 ,  H01L21/48 ,  H01L21/308

Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.

公开(公告)号：US10985057B2

公开(公告)日：2021-04-20

申请号：US16675080

申请日：2019-11-05

Applicant: IMEC vzw

Inventor： Anne Jourdain ,  Nouredine Rassoul ,  Eric Beyne

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/321 ,  H01L21/463 ,  H01L21/48 ,  H01L23/538

Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.