Invention Grant
- Patent Title: Streaming interconnect architecture for data processing engine array
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Application No.: US15944464Application Date: 2018-04-03
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Publication No.: US10990552B1Publication Date: 2021-04-27
- Inventor: Goran Hk Bilski , Peter McColgan , Juan J. Noguera Serra , Baris Ozgul , Jan Langer , Richard L. Walke , Ralph D. Wittig , Kornelis A. Vissers , Philip B. James-Roxby , Christopher H. Dick
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F13/42

Abstract:
Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.
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