公开(公告)号：US20230131698A1

公开(公告)日：2023-04-27

申请号：US18145810

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran HK Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Tim Tuan ,  David Clarke

IPC: G06F3/06 ,  G06F15/78 ,  G06F15/173

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

公开(公告)号：US11573726B1

公开(公告)日：2023-02-07

申请号：US17097917

申请日：2020-11-13

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran H K Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Christopher H. Dick ,  Philip B. James-Roxby

IPC: G06F3/06 ,  G06F15/173 ,  G06F15/78

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.

公开(公告)号：US10990552B1

公开(公告)日：2021-04-27

申请号：US15944464

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran Hk Bilski ,  Peter McColgan ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F13/40 ,  G06F13/42

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.

公开(公告)号：US11972132B2

公开(公告)日：2024-04-30

申请号：US18145810

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran H K Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Tim Tuan ,  David Clarke

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0683 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/7807

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

公开(公告)号：US11204745B2

公开(公告)日：2021-12-21

申请号：US16420831

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Akella Sastry

IPC: G06F9/44 ,  G06F8/41 ,  G06F16/901 ,  G06F9/54 ,  G06F15/78

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

公开(公告)号：US11687327B2

公开(公告)日：2023-06-27

申请号：US17695895

申请日：2022-03-16

Applicant: XILINX, INC.

Inventor： Chia-Jui Hsu ,  Shail Aditya Gupta ,  Samuel R. Bayliss ,  Philip B. James-Roxby ,  Ralph D. Wittig ,  Vinod Kathail

IPC: G06F8/41 ,  G06F16/901 ,  G06F9/54 ,  G06F11/34

CPC classification number: G06F8/433 ,  G06F9/54 ,  G06F11/3495 ,  G06F16/9024

Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

公开(公告)号：US10860766B1

公开(公告)日：2020-12-08

申请号：US16420881

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Mukund Sivaraman ,  Shail Aditya Gupta ,  Akella Sastry ,  Rishi Surendran ,  Philip B. James-Roxby ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ajit K. Agarwal ,  Ralph D. Wittig

IPC: G06F30/347 ,  G06F8/41 ,  G06F16/901 ,  G06F30/394 ,  G06F12/1081 ,  G06F115/02

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

公开(公告)号：US10802807B1

公开(公告)日：2020-10-13

申请号：US16420840

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Chia-Jui Hsu ,  Shail Aditya Gupta ,  Samuel R. Bayliss ,  Philip B. James-Roxby ,  Ralph D. Wittig ,  Vinod Kathail

IPC: G06F8/41 ,  G06F16/901 ,  G06F9/54 ,  G06F11/34

Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

公开(公告)号：US20160132441A1

公开(公告)日：2016-05-12

申请号：US14539985

申请日：2014-11-12

Applicant: Xilinx, Inc.

Inventor： Henry E. Styles ,  Jeffrey M. Fifield ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Sonal Santan ,  Devadas Varma ,  Fernando J. Martinez Vallina ,  Sheng Zhou ,  Charles Kwok-Wah Lo

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1689 ,  G06F13/28

Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

Abstract translation: 集成电路（IC）包括静态的第一区域，并且在IC和主机处理器之间提供接口。 第一区域包括具有第一主接口的第一互连电路块和具有第一从接口的第二互连电路块。 IC包括耦合到第一区域的第二区域。 第二区域实现异构多处理器设计的内核，并且包括耦合到第一互连电路块的第一主接口并被配置为从主处理器接收命令的从接口。 第二区域还包括耦合第二互连电路块的第一从接口的主接口，其中第二区域的主接口是用于存储器控制器的主站。

公开(公告)号：US20200372200A1

公开(公告)日：2020-11-26

申请号：US16420881

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Mukund Sivaraman ,  Shail Aditya Gupta ,  Akella Sastry ,  Rishi Surendran ,  Philip B. James-Roxby ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ajit K. Agarwal ,  Ralph D. Wittig

IPC: G06F30/347 ,  G06F8/41 ,  G06F16/901 ,  G06F12/1081 ,  G06F30/394

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.