公开(公告)号：US11972132B2

公开(公告)日：2024-04-30

申请号：US18145810

申请日：2022-12-22

申请人： Xilinx, Inc.

发明人： Juan J. Noguera Serra ,  Goran H K Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Tim Tuan ,  David Clarke

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F15/173 ,  G06F15/78

CPC分类号： G06F3/0647 ,  G06F3/061 ,  G06F3/0683 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/7807

摘要： A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

公开(公告)号：US11730325B2

公开(公告)日：2023-08-22

申请号：US17468346

申请日：2021-09-07

申请人： XILINX, INC.

发明人： Peter McColgan ,  Goran Hk Bilski ,  Juan J. Noguera Serra ,  Jan Langer ,  Baris Ozgul ,  David Clarke

IPC分类号： G06F21/85 ,  A47K11/02 ,  E04H1/12 ,  E04H15/38 ,  G06F13/40

CPC分类号： A47K11/02 ,  E04H1/1216 ,  E04H15/38 ,  G06F13/4022 ,  Y02A50/30

摘要： Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.

公开(公告)号：US11520717B1

公开(公告)日：2022-12-06

申请号：US17196669

申请日：2021-03-09

申请人： Xilinx, Inc.

发明人： David Clarke ,  Peter McColgan ,  Zachary Dickman ,  Jose Marques ,  Juan J. Noguera Serra ,  Tim Tuan ,  Baris Ozgul ,  Jan Langer

IPC分类号： G06F13/28 ,  G06F13/16

摘要： An integrated circuit having a data processing engine (DPE) array can include a plurality of memory tiles. A first memory tile can include a first direct memory access (DMA) engine, a first random-access memory (RAM) connected to the first DMA engine, and a first stream switch coupled to the first DMA engine. The first DMA engine may be coupled to a second RAM disposed in a second memory tile. The first stream switch may be coupled to a second stream switch disposed in the second memory tile.

公开(公告)号：US10824584B1

公开(公告)日：2020-11-03

申请号：US15944295

申请日：2018-04-03

申请人： Xilinx, Inc.

发明人： Juan J. Noguera Serra ,  Sneha Bhalchandra Date ,  Jan Langer ,  Baris Ozgul ,  Goran H K Bilski

IPC分类号： G06F9/24 ,  G06F15/177 ,  G06F15/173 ,  G06F15/80 ,  G06F9/4401

摘要： A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US11669464B1

公开(公告)日：2023-06-06

申请号：US16858417

申请日：2020-04-24

申请人： XILINX, INC.

发明人： Goran Hk Bilski ,  Baris Ozgul ,  David Clarke ,  Juan J. Noguera Serra ,  Jan Langer ,  Zachary Dickman ,  Sneha Bhalchandra Date ,  Tim Tuan

IPC分类号： G06F12/1081 ,  G06F12/06 ,  G06F9/52 ,  G06F15/78 ,  G06F12/02

CPC分类号： G06F12/1081 ,  G06F9/524 ,  G06F12/0246 ,  G06F12/0607 ,  G06F15/7807

摘要： Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.

公开(公告)号：US11336287B1

公开(公告)日：2022-05-17

申请号：US17196574

申请日：2021-03-09

申请人： Xilinx, Inc.

发明人： Javier Cabezas Rodriguez ,  Juan J. Noguera Serra ,  David Clarke ,  Sneha Bhalchandra Date ,  Tim Tuan ,  Peter McColgan ,  Jan Langer ,  Baris Ozgul

IPC分类号： H03K19/1776 ,  H03K19/17704 ,  H03K19/17768 ,  H03K19/17758 ,  H03K19/17796

摘要： An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.

公开(公告)号：US20190303347A1

公开(公告)日：2019-10-03

申请号：US15944408

申请日：2018-04-03

申请人： Xilinx, Inc.

发明人： Goran H.K. Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  David Clarke ,  Sneha Bhalchandra Date

IPC分类号： G06F15/80

摘要： An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

公开(公告)号：US20190303328A1

公开(公告)日：2019-10-03

申请号：US15944617

申请日：2018-04-03

申请人： Xilinx, Inc.

发明人： Goran H.K. Balski ,  Juan J. Noguera Serra ,  David Clarke ,  Tim Tuan ,  Peter McColgan ,  Zachary Dickman ,  Baris Ozgul ,  Jan Langer

IPC分类号： G06F13/40 ,  G06F13/16

摘要： A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.

公开(公告)号：US12105667B2

公开(公告)日：2024-10-01

申请号：US18114850

申请日：2023-02-27

申请人： XILINX, INC.

发明人： Juan J. Noguera Serra ,  Sneha Bhalchandra Date ,  Jan Langer ,  Baris Ozgul ,  Goran H. k. Bilski

IPC分类号： G06F9/24 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F1/24 ,  G06F9/4401

CPC分类号： G06F15/177 ,  G06F15/17306 ,  G06F15/80 ,  G06F1/24 ,  G06F9/4401 ,  G06F9/4411

摘要： A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US11567881B1

公开(公告)日：2023-01-31

申请号：US15944602

申请日：2018-04-03

申请人： Xilinx, Inc.

发明人： Goran H. K. Bilski ,  David Clarke ,  Baris Ozgul ,  Jan Langer ,  Juan J. Noguera Serra

IPC分类号： G06F13/10 ,  G06F13/16

摘要： A device may include an array of data processing engines (DPEs) on a die and an event broadcast network. Each of the DPEs includes a core, a memory module, event logic in at least one of the core or the memory module, and an event broadcast circuitry coupled to the event logic. The event logic is capable of detecting an occurrence of one or more events in the core or the memory module. The event broadcast circuitry is capable of receiving an indication of a detected event detected by the event logic. The event broadcast network includes interconnections between the event broadcast circuitry of the DPEs. Detected events can trigger or initiate various responses, such as debugging, tracing, and profiling.